In AI server 24–36 layer high-multilayer PCBs, stack-up planning is no longer merely about allocating signal and power layers; it is a comprehensive design endeavor involving signal integrity (SI), power integrity (PI), lamination processes, board thickness aspect ratios, and back-drilling techniques. As the necessary path for signals transitioning from surface layers to inner layers, vias represent the most significant point of impedance discontinuity in high-speed links. Stubs, annular rings, return reference planes, and via shunting—every detail impacts overall system performance. In many projects, simulations show excellent channel metrics, yet actual eye diagrams are poor; the root cause often lies in the stack-up and via design. This article analyzes the core principles of AI server stack-up design, along with the practical engineering considerations for vias and back-drilling.

I. Core Design Principles for AI High-Multilayer Stack-Ups

First, the Principle of Reference Plane Continuity. Every high-speed signal layer must be adjacent to a solid ground reference plane. A signal-ground paired arrangement is preferred, avoiding signal layers adjacent to power planes. Power planes are inherently noisy; if a high-speed signal references a power plane, resonant noise from the plane couples into the differential link, causing jitter and bit errors. In areas with power splits, high-speed differential pairs must never cross the split; doing so fractures the reference plane, distorts the return path, and causes severe impedance deviations.

Second, the Principle of Stack-Up Symmetry. Mirror symmetry in core thickness and copper weight is the golden rule for high-multilayer boards. The higher the layer count, the greater the risk of board warpage caused by asymmetric stack-ups. Post-reflow deformation in BGA areas leads to massive soldering defects. Even at the cost of some routing flexibility, lamination structure symmetry must be maintained.

Third, Matching Power/Ground Layer Count to PDN Requirements. GPUs draw massive peak transient currents; therefore, power and ground planes must be paired to increase inter-plane capacitance and lower the target PDN impedance. One must not blindly increase signal layers at the expense of power/ground layers. Power layers should prioritize 2oz heavy copper to enhance current carrying capacity and reduce DC resistance.

Fourth, Balancing Dielectric Thickness for Impedance Control and Process Limits. For high-speed differential 100Ω impedance, dielectric thickness cannot be infinitely thin. Excessively thin cores in high-layer-count boards risk dielectric shift and resin voids during lamination. Conversely, excessive thickness leads to overall board thickness violations and higher drill aspect ratios, compromising plated-through-hole reliability. Stack-up design requires simultaneous impedance simulation, board thickness calculation, and aspect ratio verification.

Fifth, Differentiating Signal Layer Copper Weights. High-speed signal layers typically use 0.5oz copper to minimize undercut and ensure better impedance consistency, while power and ground layers utilize 2oz heavy copper to achieve a differentiated copper weight stack-up.

II. Sources of Signal Degradation from Vias in AI Servers

Through-hole vias comprise pads, annular rings, plated barrel walls, and non-functional stubs. When high-speed signals traverse a via, the pad and anti-pad cause local impedance discontinuities. The stub acts as an open-circuited transmission line stub, creating resonances at specific frequencies that introduce significant insertion and return loss—making it the primary killer of 112G/224G links. While short stubs were tolerable at 25Gbps, at 56G and above with PAM4 signaling, a stub of just a few mils can cause channel failure.

Furthermore, regarding the via return path, if no nearby ground vias are present, the signal return current takes a detour, drastically increasing loop inductance and exacerbating crosstalk and noise. For high-current power vias, insufficient quantity or small diameters lead to high DC resistance, resulting in significant IR drop and severe voltage droop under dynamic loads.

Vias present two inherent conflicts: high-speed signals demand small diameters and small pads/anti-pads to minimize impedance discontinuities, while high-current power vias require larger diameters and multiple parallel vias to boost current capacity. In dense BGA areas, the congestion of high-speed signal vias, power vias, and ground vias necessitates careful trade-off in layout.

III. Engineering Design Specifications for Back-Drilling

Back-drilling is a controlled-depth drilling process used to remove the unused stub portion of a through-hole, minimizing stub length. It is an essential process for high-speed AI server PCBs. In engineering, SerDes high-speed via stubs are generally controlled within 8–12 mils; higher data rates allow for even shorter stubs.

Design-side considerations include:

Process Tolerance: Back-drilling has depth tolerance; do not set the theoretical stub length to zero—always reserve a process margin.
Clearance Rules: The back-drill diameter must be larger than the original via. The layout must reserve a back-drill exclusion zone where no traces or pads are permitted.
Selective Application: Not all vias require back-drilling. Low-speed signals and power vias do not need it; apply only to high-speed SerDes differential vias to avoid unnecessary cost increases.
Design First: Plan signal layer locations during the stack-up phase to inherently minimize stub lengths requiring removal; do not rely solely on back-drilling to fix poor stack-up design.

Back-drilling carries risks such as residual copper debris and over-drilling damaging inner layers. Manufacturers must perform CT X-ray sampling and cross-sectional microsectioning to confirm stub lengths; back-drill quality must be verified during the prototype phase.

IV. Practical Via Layout in High-Speed BGA Areas

GPUs, HBM, and switch chips feature extremely high BGA pin densities, leaving minimal via space. For high-speed differential pairs:

Prioritize fanout simulation to optimize pad and anti-pad sizes, reducing via impedance discontinuities.
Place ground vias adjacent to every signal via pair to provide a return path and lower loop inductance.
Ensure differential vias are symmetric on the same layer with identical lengths to prevent intra-pair skew.
Maintain spacing between differential vias to suppress via-to-via crosstalk.

For power pins, use multiple parallel vias and perform derated current carrying calculations. Do not rely solely on DC capacity; factor in temperature cycling and aging derating. Maintain distance between power vias and high-speed signal vias to prevent power noise coupling into high-speed links.

HBM interfaces operate at extremely high speeds and demand even stricter fanout via designs. In many scenarios, HDI (High-Density Interconnect) technology with blind and buried vias is employed to eliminate stub issues entirely, albeit at the cost of increased manufacturing complexity.

V. Summary of Common Pitfalls in Stack-Up and Via Design

Pitfall 1: Simulating trace impedance only while ignoring via-induced impedance discontinuities—vias are the primary source of high-speed channel loss.
Pitfall 2: Asymmetric high-multilayer stack-ups prioritizing routing over lamination symmetry, leading to warpage and catastrophic assembly yields.
Pitfall 3: Applying back-drilling to all vias, which increases costs and introduces risks associated with the back-drilling process itself.
Pitfall 4: Omitting ground vias adjacent to high-speed signal vias, causing long return paths, increased crosstalk, and jitter degradation.
Pitfall 5: Insufficient power vias based only on DC current capacity, ignoring IR drop under transient high-current conditions.

Conclusion

The core of AI server high-multilayer PCB stack-up design lies in the symmetric arrangement of signals, ground, and power to ensure solid reference planes for high-speed signals. Via design must focus on controlling stubs, impedance discontinuities, and return paths, utilizing back-drilling judiciously, and conducting pre-layout simulations for BGA fanout. Since stack-up and via architecture are established early in the design cycle, modifications later are prohibitively expensive. Multiple review rounds must be completed during the initial project phases.