A complete wired network communication link comprises two core transmission media: the board-level transmission channel formed by differential traces on the PCB, and the external transmission cables such as twisted-pair, coaxial cable, or optical fiber. In many hardware projects, standalone testing of the PCB Ethernet port shows perfectly normal data transmission and reception; yet once connected to finished patch cords for long-distance networking, packet loss, CRC errors, and network latency fluctuations emerge immediately. When chip and circuit diagnostics reveal no anomalies, the root cause lies in the impedance mismatch between the PCB microstrip/stripline medium and the external cable. Signal reflections generated at the junction of these two dissimilar media cause energy to backfeed into the PHY receiver inputs, resulting in erroneous signal decision thresholds. Beyond this, ESD protection, surge suppression, and interface filtering circuits alter local transmission impedance and disrupt link continuity. This article constructs an end-to-end, full-link network transmission impedance matching system from the perspective of collaborative design across three domains—PCB internal medium, interface components, and external cabling—to eliminate communication faults caused by medium transitions.

1. Standard Impedance Baseline and Isolation Transformer Transition

Ethernet standards dictate that twisted-pair differential impedance is fixed at 100Ω. Consequently, the entire differential routing segment from the PHY chip to the RJ45 receptacle on the PCB must theoretically be locked to the same 100Ω target. A common pitfall is setting a 100Ω simulation constraint while ignoring the impedance shift introduced by the isolation transformer (magnetics). The transformer windings inherently possess parasitic inductance and distributed capacitance, effectively inserting a passive network between the two transmission media. If the transformer selection parameters do not align, an impedance discontinuity forms directly between the PCB traces and the cable.

Best-practice topology: Strictly control the PHY-side differential traces to 100Ω; keep the transformer-to-receptacle side routing as short as possible rather than running long controlled-impedance lines. Rely on the internal winding characteristics of the transformer to accomplish the impedance transition, thereby preventing hard-mating reflections between two structurally different media.

2. PCB Medium Consistency: Stripline vs. Microstrip

PCB transmission media are divided into inner-layer striplines and outer-layer microstrips. Even with identical line width and spacing, there is an inherent 8%–12% impedance deviation between the two structures. If a differential pair switches from the outer layer to an inner layer mid-route before exiting to the RJ45 interface, the link essentially changes its dielectric structure mid-stream. Each impedance discontinuity point generates secondary reflections; when superimposed, the bit-error probability multiplies exponentially.

Optimal layout guidelines:

Route differential pairs on a single continuous layer all the way to the connector whenever possible.
If layer changes are unavoidable, complete the via transition near the transformer area to minimize the length of the post-discontinuity trace, weakening reflection impacts.
RJ45 receptacle pads are physically oversized. Implement tapered trace transitions at the socket pins—avoid abrupt widening or necking of the trace width—to prevent localized dielectric structure突变 (structural突变).

3. Matching Across Heterogeneous External Cables

External cabling standards vary by protocol, and PCB impedance must mirror them:

Protocol / Medium	Cable Nominal Impedance	PCB Target Differential Impedance	Termination Rule
Ethernet (Cat 5e/6)	100Ω Twisted Pair	100Ω	Handled via magnetics & center tap
RS-485 / CAN Bus	120Ω Shielded TP	120Ω	Termination resistor placed adjacent to the interface connector
Optical Fiber	Optical (No electrical Z)	N/A	Ensure solid ground pour beneath the optical module

Critical note on termination resistors: For RS-485/CAN, if the matching resistor is placed near the MCU/transceiver pins rather than right at the physical connector, the long cable and PCB trace remain unloaded. Reflected waves will oscillate back and forth along the bus, causing severe data collision in multi-node topologies.
For fiber optics, while no electrical impedance matching is needed, the reference ground beneath the photoelectric conversion module must be kept completely contiguous to suppress EMI-induced module instability.

4. The Hidden Disruptors: Protection & Filtering Devices

TVS diodes for ESD, gas discharge tubes, and common-mode filter capacitors are silent impedance killers. These protective devices are shunted between differential lines and chassis/signal ground, introducing parasitic capacitance that artificially pulls down the differential impedance. High-capacitance protection elements can locally skew the equivalent impedance far from the standard value.

Mitigation strategy:

Exclusively use Ethernet-specific TVS arrays with ultra-low junction capacitance (< 1 pF).
Place protection devices immediately adjacent to the socket pins to confine the degraded-impedance zone to the shortest possible run length.
Route the ESD discharge path into a partitioned ground plane locally; never let it hijack the primary differential return path.

5. End-to-End Design Philosophy

The cornerstone of link stability is ensuring a smooth impedance gradient across the PCB medium, isolation components, and external cable—eliminating any abrupt electrical characteristic shifts.

To institutionalize this in your workflow:

Schematic phase: Lock component parasitic parameters (transformer inter-winding capacitance, TVS junction capacitance) before layout begins.
PCB phase: Simulate and route strictly per the cable's standard impedance, not just the chip vendor's generic reference layout.
Placement phase: Anchor terminal matching elements to the physical boundary of the board.
Partitioning phase: Isolate noisy discharge loops from analog/differential reference planes.

By elevating the mindset from isolated PCB design to end-to-end transmission link architecture, the notorious "passes standalone bench test but fails in real-world cabling" syndrome is fundamentally resolved, guaranteeing long-term deterministic communication under actual deployment conditions.