In the design of high-speed interfaces such as DDR, PCIe, Gigabit Ethernet, and LVDS, controlled impedance in multilayer PCBs is no longer optional—it is a mandatory technical specification. Many hardware engineers simply equate impedance control with setting a 50Ω or 100Ω parameter, overlooking the fundamental differences between microstrip and stripline models. This oversight often leads to scenarios where simulations look perfect, yet the actual prototypes exhibit closed eye diagrams and high bit error rates (BER).
Multilayer PCB impedance is not merely an electrical value; it is a comprehensive technical specification encompassing stack-up, materials, routing, tolerances, and testing. Without clearly defined impedance requirements at the outset, even visually flawless boards can suffer from hidden high-speed link instabilities. Starting from the basics, this article outlines the core technical requirements for multilayer impedance to help engineers build a complete understanding.
1. Distinguishing Between the Two Transmission Models
Multilayer PCBs primarily utilize two transmission models: outer-layer microstrips and inner-layer striplines. Their impedance calculation formulas and influencing parameters are entirely different, meaning a single trace width setting cannot be applied universally.
Outer-Layer Microstrips: Traces on the surface have one side exposed to the dielectric substrate and the other coated with solder mask (green oil).
Inner-Layer Striplines: Traces sandwiched between two reference planes (Ground or Power).
To achieve the same target impedance (e.g., 50Ω single-ended), the required trace width and dielectric thickness for a microstrip are vastly different from those for a stripline. A common design error is copying outer-layer impedance parameters to the inner layers, resulting in significant impedance deviation. Microstrips are affected by solder mask thickness, leading to generally larger impedance tolerances. Striplines, surrounded by dielectric, are immune to solder mask variations and offer better impedance stability; therefore, critical high-speed signals should be prioritized on inner-layer striplines. Design documents must explicitly label whether a signal group uses a microstrip or stripline model—simply stating "50Ω Single-Ended" is insufficient.
2. Standard Impedance Values and Tolerance Grades
The industry has established standard impedance targets:
DDR Data Lines: 50Ω Single-Ended
USB: 90Ω Differential
HDMI, LVDS, SATA: 100Ω Differential
PCIe: 85Ω Differential
Beyond the target value, the tolerance range is a critical technical requirement.
Standard Consumer Electronics: Typically ±10%.
Industrial Equipment & Gigabit Ethernet: Usually ±7%.
High-Speed SerDes & RF Links: Tightened to ±5%.
Stricter tolerances exponentially increase the difficulty of controlling laminate materials, pressing, and etching processes, subsequently driving up costs and lead times. Engineers should not blindly pursue the tightest tolerances; instead, refer to the chip manufacturer’s datasheet. If the datasheet allows ±10%, specifying ±5% is unnecessary and wasteful. Always explicitly state the target impedance and allowed tolerance in the fabrication documents to prevent the factory from defaulting to a wider, uncontrolled range.
3. The Four Core Variables Determining Impedance
Multilayer impedance is governed by four variables:
Trace Width: Wider traces result in lower impedance.
Dielectric Height: The distance from the trace to the reference plane. A thicker dielectric (signal further from the plane) results in higher impedance.
Copper Thickness: Thicker copper slightly lowers impedance.
Dielectric Constant (Dk): Higher Dk materials result in lower impedance.
Unlike 2-layer boards, the dielectric thickness in multilayer PCBs is determined by the combination of core materials and prepreg (PP) sheets. During lamination, the PP flows and compresses, meaning the final thickness differs from the nominal thickness. This is the greatest challenge in multilayer impedance control; relying solely on basic EDA calculators is prone to error. It is recommended to use professional impedance tools like Polar Si9000, incorporating the actual material parameters provided by the manufacturer. For differential impedance, pair spacing is an additional critical variable—variations in spacing directly alter the differential impedance value.
4. Impedance Documentation: What Information Must Be Provided to the Fab
Many impedance failures stem from engineers simply emailing a note saying, "Please control impedance at 50Ω," without providing a formal specification. A qualified Impedance Control Table or Specification must include:
Impedance Network List: The specific nets or groups requiring control.
Signal Layers: The physical layer location.
Model Type: Microstrip or Stripline.
Target Impedance & Tolerance.
Stack-up Details: Specific core/PP material types and nominal thicknesses.
Copper Weight.
Laminate Specifications: Material brand, model, and Dk values at the operating frequency.
Routing Geometry: Trace width and coupling spacing for differential pairs.
Test Requirements: Whether a Time Domain Reflectometry (TDR) test report is required.
Do not rely solely on Gerber files. Impedance is a special process requirement that demands a dedicated instruction document. Providing complete data allows the factory to verify the stack-up and pre-adjust parameters before production.
5. Common Misconceptions in Multilayer Impedance Design
Misconception 1: Assuming calculation is the end of the process and ignoring reference plane integrity. The reference plane beneath an impedance-controlled trace must be continuous. If a signal crosses a split in the ground plane, the transmission line model is destroyed, causing severe impedance discontinuities, regardless of correct trace width.
Misconception 2: Using the same trace width for both inner and outer layers, ignoring the physical differences between microstrips and striplines.
Misconception 3: Focusing only on differential impedance while ignoring single-ended odd/even mode impedances. If the single-ended impedance of the two lines in a differential pair is mismatched, common-mode noise is introduced, worsening EMI radiation.
Misconception 4: Ignoring manufacturing process variations by setting trace widths at the absolute process limit. Minor etching deviations can then push the impedance out of specification.
Controlled impedance is not just about filling in a number; it is a complete technical framework involving models, targets, tolerances, materials, and documentation synergy. Defining these requirements clearly at the beginning is the key to reducing hidden faults during prototype debugging.
Home > 
