In the design of high-speed circuits, RF, communications, and precision industrial control products, impedance control in 4-layer PCBs is a core factor determining signal integrity. As electronic products trend toward higher frequencies, smaller sizes, and faster speeds, relying solely on empirical routing can no longer meet design requirements. Precise impedance calculation and matching have become essential skills for hardware engineers and PCB designers. As the most common multilayer board structure in industrial applications, 4-layer boards balance cost, performance, and process difficulty. Their impedance calculation logic differs from that of single/double-sided boards and also from high-order 6-layer or 8-layer boards. Clarifying the basic formulas and key parameters is the first step toward effective impedance design.

First, it is essential to define the classic stack-up structure of a 4-layer board. The conventional 4-layer board consists, from top to bottom, of the Top Signal Layer, Inner Ground Layer, Inner Power Layer, and Bottom Signal Layer—commonly referred to as the S1-GND-VCC-S2 structure. This stack-up is the mainstream layout for impedance control; the top and bottom layers serve as external signal routing layers, while the two middle layers act as solid ground and power planes, forming a stable transmission line structure via the dielectric layers. PCB transmission lines are primarily divided into two categories: Microstrip Lines and Striplines. In a 4-layer board, traces on the top and bottom layers correspond to microstrip lines, whereas traces routed on inner signal layers constitute striplines. Their calculation formulas and influencing parameters are entirely different, serving as the fundamental basis for impedance calculation.

Dielectric material parameters form the foundation of impedance calculation, with the Dielectric Constant (Dk) carrying the highest weight. For commonly used FR-4 laminates, the typical Dk ranges between 4.2 and 4.5, though values fluctuate depending on the brand, sheet thickness, and operating frequency. The dielectric constant may also decrease slightly in high-frequency scenarios; using standard values directly will result in deviations in the final measured impedance. Next is the dielectric thickness (H), which refers to the distance from the trace copper to the reference plane. In 4-layer boards, the dielectric thickness from the top copper foil to the GND layer and from the bottom copper foil to the VCC layer must be strictly defined according to the stack-up design. Generally, greater dielectric thickness results in higher transmission line impedance. Copper thickness (T) is also critical; industry-standard weights include 1oz and 0.5oz. Thicker copper increases the cross-sectional area of the trace, thereby lowering impedance. Additionally, copper surface roughness can affect impedance accuracy at high frequencies.

Next, let’s discuss the basic calculation formulas for microstrip lines. Microstrip lines are the dominant form of surface routing on 4-layer boards and are categorized into Surface Microstrips and Covered (Solder Mask) Microstrips. The classic empirical formula for an uncovered microstrip, suitable for general precision designs, is:

Z0≈Dk+1.4187×ln(0.8W+T5.98H)

Where $H$is the dielectric thickness, $W$is the trace width, and $T$is the copper thickness. When surface traces are covered with solder mask ink, the equivalent dielectric constant increases, causing the impedance to drop by approximately 3% to 8%. This must be factored into calculations for high-frequency and high-speed circuits. Many junior engineers overlook the impact of the solder mask layer, applying the bare copper microstrip formula directly, which leads to post-production impedance exceeding specifications and causing signal reflection and jitter issues.

Striplines are primarily applied to inner layer routing scenarios in 4-layer boards. When a signal is routed in the region between the GND and VCC layers, it forms a symmetric stripline. The impedance formula for a symmetric stripline is:

Z0≈Dk60×ln(0.67πW(0.8+T/W)4H) or simplified versions like Dk30×ln(0.8W+T8H)

Here, $H$is the total dielectric thickness between the upper and lower reference planes. Comparing this to the microstrip formula reveals that, under identical width and dielectric parameters, stripline impedance is generally lower than that of microstrips. Furthermore, striplines offer superior shielding and anti-interference capabilities; therefore, high-frequency sensitive signals should preferably be laid out as inner-layer striplines.

In practical calculation workflows, engineers should follow these fixed steps:

Numerous pitfalls exist in daily design, such as mixing dielectric constants from different materials, ignoring changes in copper thickness, or failing to distinguish between single-ended and differential lines. Differential impedance cannot be derived simply by applying single-ended transmission line formulas; the spacing between the two traces ($S$) must be calculated separately—smaller spacing results in lower differential impedance. For 4-layer boards, a complete mid-layer ground plane is the guarantee of impedance stability. If the ground plane is heavily voided or split, the transmission line reference return path is disrupted, causing actual impedance to drift severely even if theoretical calculations were precise.

Impedance calculation for 4-layer PCBs is not merely a mathematical exercise but a comprehensive design task integrating circuit requirements, material characteristics, PCB stack-up, and production processes. At the introductory stage, mastering the two core formulas for microstrip and stripline lines and controlling the four major parameters—dielectric constant, dielectric thickness, trace width, and copper thickness—is sufficient to complete impedance calculations for the vast majority of conventional products. For high-speed digital and RF circuits, secondary verification using simulation software is required to perfectly align theoretical calculations with actual production, mitigating signal integrity issues at the source.