Thermal vias and exposed pads serve as the "vertical high-speed channels" for transferring heat from the surface layer to inner and bottom layers in high-power PCBs. They act as the critical bridge connecting heat sources to large copper areas, and their design quality directly determines thermal conductivity efficiency and thermal resistance. Poorly designed thermal vias and pads can lead to heat accumulation beneath components, creating localized hot spots that render external heatsinks ineffective. Conversely, scientific design significantly reduces thermal resistance and accelerates heat dissipation. As a core technique in "path-based cooling," precise control over dimensions, quantity, layout, and process details is essential.
Exposed Pad (Thermal Pad) Design
The exposed pad is the "thermal interface" between power devices and PCB copper; its core function is to maximize contact area and minimize interface thermal resistance. For high-power packages (QFN, DFN, D²PAK, TO-220, etc.) with exposed thermal pads, adhere to these guidelines:
Maximize Pad Size: The thermal pad area should be ≥ 1.2 times the size of the component's exposed thermal area. Extend the pad into surrounding blank areas to increase contact with copper pours. Example:For a QFN 5×5 package, designing a 6×6 mm pad increases the thermal contact area by 44%.
Pad Opening (Soldermask): Use an NSMD (Non-Solder Mask Defined) design. Ensure the soldermask clears the thermal pad area to expose bare copper. This facilitates heatsink attachment or TIM (Thermal Interface Material) application and avoids the high thermal resistance of soldermask.
Solid Copper Pour: Use solid copper pours (2oz or thicker) beneath and around the pad. Avoid hatched/dotted copper, ensuring rapid heat spreading. Connect the pour directly to power or ground planes to form a continuous thermal path.
Stencil Design: Apply step-down or thickness-reduced stencil apertures for the thermal pad to control solder paste volume. This prevents voiding caused by excessive paste. Target:Void rate < 5% to minimize interface resistance.
Thermal Via Design
Thermal vias are "vertical channels" transferring heat from the surface pad to internal or bottom layers. Their purpose is to bridge the vertical thermal path and reduce Z-axis resistance. Key parameters include:
Aperture Selection: Prioritize small diameters of 0.2–0.3 mm. Smaller vias allow higher density, increasing total thermal transfer area. Oversized vias (>0.4mm) risk solder wicking and voids; undersized vias (<0.2mm) are difficult to plate reliably.
Pitch Control: Maintain a via pitch of ≤ 1.0 mm. Arrange them in a dense array to ensure uniform heat transfer. Excessive spacing creates high-resistance islands.
Quantity Configuration: Base the number of vias on device power dissipation:
Layout: Distribute vias evenly across the thermal pad, avoiding component pins to prevent shorts. Place vias more densely in the center and slightly sparser at the edges to facilitate radial heat spreading.
Process Requirements: Use copper-filled vias (not resin-plugged). Ensure the plated copper thickness inside the via barrel is ≥ 20 μm to guarantee electrical and thermal continuity. Filling eliminates air gaps, significantly boosting conductivity.
Combined Design Case Study
Scenario: A QFN 5×5 packaged MOSFET with 25W power dissipation.
Design: A 6×6 mm exposed copper pad is implemented. Beneath it, a 6×6 array of 36 thermal vias (0.3mm diameter, 1mm pitch) is placed.
Stack-up: Vias are copper-filled and connect to a 2oz thick, solid copper inner GND plane.
Result: Large copper pours are added on both the top and bottom layers. This forms a complete channel: Surface Pad → Thermal Vias → Inner GND → Bottom Layer Copper.
Performance: Measured junction temperature dropped from 130°C to 95°C, demonstrating significant effectiveness.
Common Pitfalls and Mitigation
Pitfall | Consequence | Mitigation |
|---|
Insufficient Quantity | Low thermal conductivity, high resistance. | Configure based on power; use dense arrays. |
Incorrect Aperture | >0.4mm causes solder wicking; <0.2mm is hard to manufacture. | Prefer 0.25–0.3 mm. |
Resin Plugging | Resin has poor thermal conductivity. | Must use copper filling for conductivity. |
Masked Pad | Soldermask adds thermal resistance. | Use NSMD, expose bare copper. |
Proximity to Pins | Risk of short circuits. | Keep clear of pin areas; distribute evenly. |
Conclusion
Thermal vias and exposed pads are the "core bridges" of high-power PCB thermal management. The design philosophy centers on "Large Pads, Dense Vias, Copper-Filled, Bare Copper Surface." By maximizing thermal contact area, constructing efficient vertical channels, and strictly controlling process quality, designers can drastically reduce thermal resistance. Mastering these techniques is key to enhancing PCB cooling capacity and preventing localized hotspots.
Home > 
