Once the base material is selected, the stack-up structure becomes the second core pillar of high-frequency and high-speed PCB design. The logic used for standard PCB stack-ups cannot be directly applied to high-frequency/high-speed products. The stack-up dictates impedance control, signal return paths, crosstalk levels, and power integrity. In many projects, simulations look ideal, but the fabricated boards show degraded eye diagrams—the root cause is often irrational stack-up planning.
Core Design Principles for High-Frequency/High-Speed Stack-ups
First, ensure signal layers are adjacent to a continuous reference ground plane. High-speed differential traces and RF microstrip/stripline must have a complete, uninterrupted reference plane. Discontinuous return paths lead to significant signal loss, reflections, and EMI radiation—the number one killer in high-frequency design.
Second, maintain structural symmetry. Asymmetry in dielectric thickness or copper weight across the layers causes severe warpage after lamination. For high-layer-count HF/HS boards, warpage leads to poor SMT placement and BGA solder joint failures.
Third, distinguish between microstrip and stripline applications. Microstrips are on the surface layer (one side air, one side dielectric), making them suitable for RF; however, surface signals are susceptible to external interference and radiation. Striplines are buried between two ground planes, offering excellent shielding and stable loss, making them ideal for high-speed differential signals, albeit at the cost of consuming more layers.
Fourth, for impedance calculations, always use the measured wideband Dk parameters provided by the laminate vendor; do not rely on default FR-4 values. The same trace width will yield different impedances depending on the Dk, and deviations will cause excessive signal reflection.
Analysis of Typical Stack-up Schemes
8-Layer High-Speed Digital Board (AI Accelerator, Switch):
Recommended structure: Signal‑GND‑Signal‑PWR‑GND‑Signal‑GND‑Signal. Route high-speed signals as striplines, sandwiched between solid ground planes. Place power planes adjacent to ground planes to enhance power-ground coupling and improve PDN impedance.
4-Layer High-Frequency Hybrid Board (Optical Module):
Top Layer (RF Microstrip) – L2 (Solid Ground) – L3 (Power) – Bottom Layer (General Digital Signals). Route all RF traces on the top layer, referencing the solid ground on L2. Avoid crossing power splits.
For mixed-signal boards containing both RF and ultra-high-speed digital signals, allocate them to different signal layers. Ensure their vertical projections do not overlap significantly to minimize inter-layer coupling and crosstalk.
Note: Never use a split power plane as a reference for a high-speed signal layer. If a trace crosses a split, the return current is forced to detour, causing impedance discontinuity and severe signal integrity degradation.
Via Management: The Biggest Impedance Discontinuity
Vias represent significant impedance discontinuities in high-frequency links. Via stubs, parasitic capacitance, and inductance increase return loss, especially at high frequencies.
For data rates above 25 Gbps, prioritize back-drilling to remove unused via stubs. For HDI products, use blind and buried vias to eliminate stubs entirely. Via-in-pad with resin filling is recommended for high-density BGA fan-outs to reduce signal loss.
Via anti-pad size must be calculated precisely. Too small an anti-pad increases parasitic capacitance; too large disrupts the integrity of the reference ground copper. When a high-speed signal changes layers, place a ground via nearby to provide a return current path and mitigate signal degradation.
Never allow asymmetry between the two vias in a differential pair. Via pads and anti-pads must be identical; otherwise, intra-pair skew increases and common-mode noise rises.
Routing and Impedance Control Best Practices
Target differential impedance is typically 100Ω, while RF single-ended is 50Ω. For HF/HS boards, standard impedance tolerance is ±5%; millimeter-wave RF scenarios may demand ±3%, far stricter than the standard ±10% for conventional PCBs.
Strictly control intra-pair length matching. Tolerances vary by speed: for PCIe 5.0, keep skew within ±5 mils. The higher the data rate, the tighter the matching requirement. Maintain sufficient spacing between differential pairs, following the 3W rule to reduce crosstalk and avoid long parallel runs.
Minimize vias on RF traces. Prioritize keeping RF microstrips on the surface rather than routing them as inner-layer striplines, as layer changes introduce impedance discontinuities. Use arcs for RF trace corners instead of 90-degree bends to minimize reflections.
For power distribution, PDN design is critical. Ensure tight coupling between power and ground layers and place decoupling capacitors close to the load. Do not split the ground plane for high-speed signals; rely on layout partitioning for digital and analog separation rather than cutting the ground plane.
Common Oversights in High-Frequency/High-Speed Design
Failing to verify the stack-up with the fabrication house. Some dielectric thickness combinations may not be available in the factory's prepreg (PP) inventory, making impedance control impossible and forcing a redesign.
Ignoring the Glass Weave Effect. In ultra-high-speed links, if traces run parallel to the glass weave, impedance varies along the length of the trace. If possible, account for this effect during simulation and design.
Lack of solder mask control on surface RF traces. Solder mask covering RF microstrips alters the effective dielectric constant, shifting the impedance. Consider solder mask stripping (opening the mask) over RF microstrip areas.
Relying solely on schematic-level simulation without incorporating the actual PCB stack-up, via models, and material parameters into channel simulations. Over-idealized models lead to a massive gap between simulation results and physical reality.
Conclusion
The stack-up defines the upper limit of board performance. Even with perfect routing, a flawed stack-up cannot be fully remedied during later debugging stages.
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