With the widespread adoption of technologies such as 5G communications, artificial intelligence, and high-speed storage, the operating frequencies of electronic devices continue to rise. Chip clock frequencies have advanced from the MHz range to the GHz range, making high-frequency and high-speed scenarios the greatest challenge in multilayer PCB power integrity design. In low-frequency circuits, the impedance and parasitic parameters of power and ground planes have negligible effects. However, in high-frequency scenarios, even slight parasitic inductance or impedance mismatches can trigger severe power supply noise and voltage fluctuations, leading to system failure.

The core pain points of power integrity in high-frequency and high-speed circuits stem from transient current surges and the exacerbation of parasitic parameters. Transistors inside high-speed chips switch within nanoseconds, drawing large currents instantly and forming steep transient current pulses. These pulses propagate through the Power Delivery Network (PDN), causing voltage droop. Simultaneously, at high frequencies, parasitic inductance and capacitance in PCB traces, vias, and plane edges are magnified. Inductance that is negligible at lower frequencies presents high impedance at high frequencies, blocking transient current transmission and disrupting chip power supply. Additionally, crosstalk from high-frequency signals and ground bounce (simultaneous switching noise) are significantly amplified. Ground bounce amplitude can even exceed signal amplitude, directly causing chip logic errors.

Addressing high-frequency power integrity issues primarily involves full-frequency-band PDN impedance matching, which is the core of high-frequency PI design. In the low-frequency range (up to a few kHz), impedance is primarily determined by the power module and large filtering capacitors, which provide continuous high-power supply. The mid-frequency range (from tens of kHz to tens of MHz) is handled by medium-capacity capacitors, compensating for moderate-speed current variations. The high-frequency range (above tens of MHz) relies on small decoupling capacitors and distributed capacitance between power and ground planes, addressing nanosecond-level transient currents. The goal of power integrity design is to ensure that PDN impedance remains below the target impedance across all frequency bands, avoiding impedance peaks and preventing noise amplification due to resonance.

Decoupling capacitor selection and layout are the core means of suppressing high-frequency noise and a common area where designers make mistakes. High-frequency decoupling capacitors should not be randomly added; they must be designed according to the principles of "capacitance value matching, proximity placement, and package suitability." First, for capacitance value matching, a combination of "large electrolytic capacitors + medium ceramic capacitors + small high-frequency capacitors" is used. Large capacitors handle low-frequency energy storage, medium capacitors address mid-frequency compensation, and small capacitors (0.1μF, 0.01μF) are responsible for high-frequency decoupling, optimizing impedance across the full frequency range. Second, in terms of layout, high-frequency small capacitors must be placed as close as possible to the chip's power and ground pins, with lead lengths controlled within 1mm. This is because, at high frequencies, the parasitic inductance of the leads far exceeds the capacitor's own inductance, and excessively long leads can render decoupling completely ineffective.

Capacitor package and material are also critical. In high-frequency scenarios, small package ceramic capacitors such as 0402 and 0201 are preferred, as their smaller parasitic inductance ensures better high-frequency response. Materials like X7R and X5R are chosen for their high-temperature stability and minimal capacitance drift, avoiding materials with high-temperature drift like Y5V. Additionally, grounding vias for decoupling capacitors should be placed directly on the capacitor pads, avoiding trace connections to further reduce parasitic inductance. For high-speed chips with BGA packages, decoupling capacitors should be placed between the pads under the chip to achieve the shortest path of "chip pin - capacitor - via - ground," maximizing high-frequency decoupling effectiveness.

Ground bounce (SSN) is the most persistent power integrity issue in high-frequency and high-speed circuits. It occurs when multiple I/O pins of a chip switch simultaneously, inducing voltage in the parasitic inductance of the ground path, causing fluctuations in the ground plane potential and affecting the chip's internal power supply. Key methods to suppress ground bounce noise include: first, increasing the number of chip ground pins and using multiple ground pins in parallel to reduce ground parasitic inductance; second, adopting dual or multiple ground planes in multilayer PCBs to further lower ground impedance; third, avoiding parallel routing of high-speed signals and power traces to reduce crosstalk-induced noise superposition; and fourth, adding ferrite beads at the chip's power entry point to isolate high-frequency noise from entering the power module.

Moreover, optimization of power and ground planes in high-frequency scenarios cannot be overlooked. Efforts should be made to minimize the dielectric thickness between power and ground planes, increase interlayer distributed capacitance, and utilize plane capacitance to replace some high-frequency decoupling capacitors for passive filtering. Additionally, long slots and large holes should be avoided on power and ground planes, especially in areas directly under the chip, to prevent interruption of high-frequency current paths. For high-speed circuits operating at GHz levels, impedance simulation is also necessary. Specialized software should be used to simulate PDN impedance curves, predict impedance peaks in advance, and adjust capacitor layouts and plane designs accordingly, avoiding issues during later prototype debugging.