Driven by AI computing power and 5G communications, specifying impedance requirements when ordering a PCB has evolved from a simple matter of "controlling trace width" into a full-fledged signal-integrity engineering task. In the past, with a 4-layer board, hitting 50 Ω was easy. Today, with 20-layer high-multi-layer HDI boards, the slightest mismatch in impedance control can break the signal link.
1. From Single-Point to Board-Wide Impedance Control
In the past, impedance specs only covered a handful of traces near the USB connector. On today's server motherboards, high-speed signals are everywhere.
Then: Simply write "USB 90 Ω".
Now: You must specify "DDR4 DQ 40 Ω, PCIe Gen4 85 Ω, Backplane 100 Ω."
The modern spec must include the Net Name. This lets the fabricator pick out the critical nets from tens of thousands of traces and apply tight control where it matters.
2. The Material Challenge: Dk and Df
In high-frequency designs, the biggest variable in any impedance spec is the laminate material.
Standard FR-4 has a Dk (dielectric constant) that drifts between 4.2 and 4.6. Push the frequency higher and the impedance starts to drift with it. Today's specs call for low-loss laminates and state the Dk test frequency explicitly — for example, "Dk 3.5 @ 10 GHz." This forces the fabricator to use genuine high-frequency copper-clad laminate (CCL) at the stack-up stage, not swap in commodity FR-4.
3. Backdrilling and the Stub Effect
For high-speed backplanes, impedance control covers not just trace width but also via stub length.
Modern specs carry a "Back Drill" note. Example: "Through-hole via L1–L10, back-drill starting from L11." The goal is to remove the unused copper barrel and suppress signal reflections. This must be called out in the drill file itself — a line in the general remarks won't cut it.
4. Closing the Loop: Simulation and Measurement
The leading-edge practice is to submit a simulation report alongside the impedance requirements.
The fabricator is no longer just "building to the drawing" but "building to the simulated parameters." Your impedance spec must include the theoretical values computed by tools such as HFSS or Sigrity. After fabrication, the shop measures S-parameters with a VNA (Vector Network Analyzer) and correlates them against the simulation. This is the highest maturity level of impedance specification today.
FAQ
Q: For high-frequency boards, do I need to specify the copper foil type in the impedance requirements?
A: Yes. At high frequencies, the skin effect dominates, so you should call out low-profile copper foil (RTF/HVLP). Otherwise insertion loss will be too high.
Q: How do I determine the back-drill depth?
A: A common rule of thumb is:
Back-drill depth = Board thickness − depth to target layer − 0.2 mm (safety margin).
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