**Stackup Design: The Soul of Controlled-Impedance PCBs**  

For the same target impedance, different stackups can lead to cost differences exceeding 30% and drastically different yields.

---

### **I. Five Core Principles of Stackup Design (Must Be Followed)**  

Regardless of the layer count, stackup design must adhere to these five fundamental rules; otherwise, impedance issues are inevitable:

1. **Controlled-impedance traces must be adjacent to a solid reference plane**  

   There should be only one dielectric layer (core dielectric) between the trace and its reference plane. Cross-layer referencing is prohibited, as it leads to unstable impedance and messy return paths.

2. **Layer sequence should be as symmetrical as possible**  

   Symmetrical stackups reduce lamination warpage, ensure uniform dielectric thickness, improve impedance consistency, and lower soldering deformation risks. Asymmetric stackups should only be used for special current-carrying or thermal dissipation needs, with warpage risks carefully evaluated.

3. **Core dielectric thickness determines impedance sensitivity**  

   The dielectric thickness (H) between the trace and its reference plane directly affects sensitivity:  

   - Thinner H increases sensitivity to thickness variation, making tolerance control difficult.  

   - Thicker H reduces sensitivity but requires narrower trace widths, making etching tolerance more critical.  

   Engineers must balance **"thickness sensitivity"** and **"trace width manufacturability."**

4. **Power and ground layers should be adjacent to form a large-plane capacitance**  

   Adjacent power and ground layers reduce power impedance and noise, which is critical for high-speed circuit stability. This also facilitates impedance referencing and return current management.

5. **Align with the PCB manufacturer’s process capabilities**  

   Different manufacturers have varying capabilities in minimum trace/space, minimum dielectric thickness, and lamination processes. Stackup design must not rely solely on theoretical calculations but must incorporate the manufacturer's actual capabilities. Otherwise, prototypes may work, but mass-production yields will plummet.

---

### **II. 4-Layer Impedance Boards: Classic Structure for Low-Cost Solutions**  

4-layer boards are the most common impedance-controlled structure in consumer electronics and industrial controls, offering significantly lower cost than 6-layer boards. With proper design, they can fully meet requirements for 50Ω single-ended and 90/100Ω differential impedance.

**Classic Structure 1 (Recommended): Top – GND – Power – Bottom**  

- Layer order: S1 (Top) – GND (S2) – Power (S3) – S4 (Bottom)  

- Impedance traces: Typically placed on Top and Bottom layers, referenced to S2 (GND) and S3 (Power)  

- Dielectric: Thin dielectric between S1-S2 (e.g., 4–6 mil), thick dielectric between S2-S3 (e.g., 20–30 mil), S3-S4 same as S1-S2  

- Advantages:  

  - Top/Bottom impedance traces reference solid planes for stable impedance.  

  - Symmetrical layer order minimizes warpage.  

  - Adjacent GND and Power layers reduce power noise.  

  - Low cost and mature process.

**Classic Structure 2 (Suitable for Simple Signals): Top – Sig – GND – Bottom**  

- Layer order: S1 – S2 – GND (S3) – S4  

- Impedance traces: S1 referenced to S3, S4 referenced to S3. S2 has no reference (not for impedance traces).  

- Application: Low-speed impedance lines or simple control boards with the lowest cost. S2 should not carry high-speed impedance traces.

**Key for 4-layer impedance design:** Place impedance traces on outer layers, referencing inner solid ground/power planes. Avoid routing impedance traces on inner layers, as dielectric control for inner layers is more difficult and costly.

---

### **III. 6-Layer Impedance Boards: Balanced Performance and Cost Structure**  

6-layer boards are the workhorse for communications, industrial controls, and mid-to-high-end consumer electronics, offering more impedance routing flexibility without excessive cost.

**Structure 1: Symmetrical Stackup (Recommended for Best Impedance Stability and Yield)**  

- S1 – GND (S2) – S3 – S4 – GND (S5) – S6  

- Impedance traces: S1 referenced to S2, S6 referenced to S5. S3/S4 for general signals.  

- Dielectric: Thin dielectric between S1-S2 and S5-S6 (4–6 mil), thick dielectric in the middle.  

- Advantages: Symmetrical, low warpage, consistent impedance, excellent GND shielding.

**Structure 2: 6-Layer with Power Plane**  

- S1 – GND – S3 – Power – S5 – GND – S6 (simplified as 6 layers: S1-GND-S3-Power-S5-S6)  

- Application: Scenarios requiring multiple power rails and low noise.  

- Note: The Power plane can serve as a reference plane but must remain solid; excessive splitting can cause impedance discontinuity.

**Advantages of 6-layer boards:** Inner layers can act as shielding to reduce crosstalk. Impedance traces can be distributed more flexibly, supporting multiple high-speed differential pairs (e.g., USB + HDMI + Ethernet).

---

### **IV. 8-Layer Impedance Boards: Stackup Logic for High-End Products**  

8-layer boards are commonly used in servers, communication base stations, and high-end RF applications. The stackup is more complex, focusing on **"multiple reference planes + symmetry + low noise."**

**Typical Symmetrical Structure:**  

S1 – GND – S3 – S4 – GND – S6 – S7 – GND – S8 (simplified as 8 layers)  

- Multiple GND layers allow impedance traces on S1, S3, S6, and S8, referenced to adjacent GND.  

- Power planes are embedded internally, adjacent to GND layers to reduce impedance and noise.  

- Dielectric thickness is strictly controlled to achieve multiple target impedances (50/90/100Ω) simultaneously.

**Cost considerations for 8-layer boards:** Costs arise from layer count, lamination cycles, and materials. Engineers should allocate impedance layers wisely, avoiding unnecessary thin dielectrics and high-speed materials to control costs effectively.

---

### **V. How to Choose Dielectric Thickness? The Balance Between Impedance and Cost**  

Dielectric thickness (H) is a core variable in stackup design. Taking FR-4, 1oz copper, and 50Ω single-ended as an example:  

- **H = 4 mil:** Trace width ~4–5 mil. Narrow traces are more sensitive to etching tolerances and impedance variation. Suitable for high-density designs.  

- **H = 6 mil:** Trace width ~6–7 mil. More process-friendly, higher yield, moderate cost.  

- **H = 8 mil:** Trace width ~8–9 mil. Easier to manufacture but occupies more space. Suitable for low-density boards.

The same principle applies to 90Ω/100Ω differential pairs: Thinner dielectrics allow smaller trace/space, enabling higher density but increasing process difficulty.

---

### **VI. Common Pitfalls in Stackup Design (Engineers Must Avoid)**  

1. **Split or slotted reference planes:** Impedance traces crossing splits cause abrupt impedance changes and severe signal reflection.  

2. **Asymmetric stackups with large thickness variations:** Lead to lamination warpage, uneven dielectric thickness, and impedance drift.  

3. **Excessive impedance traces on inner layers:** Inner-layer dielectric control is difficult, costly, and lowers yield. Prioritize outer layers for impedance traces.  

4. **Not validating stackup with the manufacturer:** Theoretical calculations may not align with the manufacturer's lamination capabilities, requiring multiple prototype revisions.  

5. **Ignoring copper thickness effects:** Designing with 1oz but producing with 2oz copper results in lower impedance.

---

### **VII. Practical Workflow for Stackup Design (Ready to Apply)**  

1. Determine layer count, impedance targets, copper thickness, and material.  

2. Draft a symmetrical layer sequence and define reference plane positions.  

3. Assign dielectric thicknesses, prioritizing the manufacturer's standard offerings.  

4. Use impedance calculation tools to verify trace width/space meet targets.  

5. Check for symmetry, reference plane integrity, and adjacent power/ground layers.  

6. Deliver stackup drawings, dielectric specifications, and impedance tables to the manufacturer for review.  

7. Fine-tune based on manufacturer feedback and finalize the stackup.

---

**Stackup design is not merely about "drawing layers"; it is a systematic trade-off among impedance, cost, manufacturability, and yield. If a 4-layer board suffices, never blindly opt for 6 layers. If standard materials meet requirements, never unnecessarily specify high-speed materials.**