Impedance Control and Material Selection Techniques for Multilayer PCB Lamination Stack-up
In high-speed/high-frequency PCB design, impedance control is the core objective of stack-up design, and the selection of lamination dielectric materials along with thickness design are the keys to achieving precise impedance control. Many engineers overlook the relationship between dielectric properties and impedance during stack-up design, leading to impedance deviation beyond specification (> ±5%) after lamination, which causes issues like signal reflection, crosstalk, and transmission errors. This article analyzes the techniques for impedance control in multilayer PCB lamination from three aspects: the principle of impedance control, material selection, and lamination stack-up parameter design.
I. Basic Principles of Impedance Control in Lamination Stack-up
High-speed signals travel on PCBs as microstrip lines (outer layers) or striplines (inner layers). Their characteristic impedance is determined by the dielectric constant (Dk) of the material, dielectric thickness (H), trace width (W), and copper thickness (T). The core formulas are as follows:
The goal of impedance control is to stabilize the characteristic impedance within ±5% of the target value (for general high-speed) or ±3% (for high-frequency RF). Common target values are 50Ω for single-ended and 100Ω for differential pairs. From the formulas, it's evident that the dielectric constant (Dk) and thickness (H) are the core variables affecting impedance. Lamination stack-up design must prioritize control over these two parameters.
II. Selection Criteria and Property Comparison of Lamination Dielectrics
Lamination dielectrics include core (Core) and prepreg (PP). Their materials must be compatible to ensure uniform and stable Dk after lamination.
General Application (< 5GHz) Material Selection
Core/PP Material: Standard FR-4, Dk=4.4±0.2 (at 1GHz), Df=0.02. Low cost, good processability.
Thickness Selection: Outer layer microstrip H=0.2~0.3mm, inner layer stripline H=0.15~0.2mm. Balances impedance accuracy and process feasibility.
Application Scenarios: 1Gbps~5Gbps high-speed digital circuits, general industrial control boards.
High-Frequency Application (≥5GHz) Material Selection
Core/PP Material: High-frequency specialized laminates (e.g., Rogers 4350B, Isola 370HR, PTFE), Dk=2.2~3.5 (at 10GHz), Df=0.001~0.004. Low loss and stable Dk at high frequencies.
Thickness Selection: Outer layer H=0.127~0.254mm (tight tolerance ±0.01mm), inner layer H=0.1~0.15mm. Strictly controls impedance fluctuation.
Application Scenarios: 5G RF modules, WiFi 7, high-speed communication boards above 10Gbps.
Key Points to Avoid in Material Selection
Core and PP materials must be compatible: Avoid mixing FR-4 core with high-frequency PP, as it causes uneven Dk after lamination and excessive impedance deviation.
Strictly control Dk tolerance: Standard FR-4 Dk tolerance ≤ ±0.2, high-frequency laminates ≤ ±0.1, to ensure impedance consistency.
Prioritize temperature coefficient: Choose materials with a Dk temperature coefficient ≤ ±50ppm/°C to maintain impedance stability in wide temperature ranges (-40°C to +85°C).
III. Impedance Matching Parameter Design for Lamination Stack-up (Practical Techniques)
Using a 6-layer high-speed board (single-ended 50Ω, differential 100Ω, FR-4 material) as an example, detailed parameter design is explained:
Layer Stack-up Planning (Symmetrical Structure): Top (Signal, Microstrip) → PP (H1=0.2mm) → GND (1oz) → PP (H2=0.15mm) → PWR (1oz) → PP (H2=0.15mm) → GND (1oz) → PP (H1=0.2mm) → Bottom (Signal, Microstrip).
Trace Width Calculation (50Ω single-ended, FR-4 Dk=4.4, 1oz Copper)
Outer Layer Microstrip (H=0.2mm): Substituting into the formula yields trace width W ≈ 0.22mm (tolerance ±0.01mm).
Inner Layer Stripline (H=0.15mm, with dielectrics above/below): Trace width W ≈ 0.18mm (tolerance ±0.01mm).
Impedance Compensation Design
Lamination Pre-compensation: Considering dielectric compression during lamination (compression rate 5%~8%), increase the design H by 5%. E.g., for a target 0.2mm, design 0.21mm.
Trace Width Pre-compensation: Accounting for an etch undercut of 0.02mm, increase the design trace width by 0.02mm to ensure the finished trace width meets the target.
Verification and Optimization
Simulation Verification: Use tools like ADS or HFSS to sweep dielectric thickness and Dk tolerance, confirming impedance fluctuation ≤ ±4%.
Trial Production Calibration: Conduct small-batch trial production, perform TDR testing to measure impedance, fine-tune dielectric thickness and trace width, and finalize parameters.
IV. Common Misconceptions in Impedance Control for Lamination Stack-up
Ignoring dielectric compression rate: Using target thickness directly without accounting for 5%~8% compression during lamination, resulting in higher-than-expected impedance.
Mismatched core and PP materials: Causes uneven Dk, leading to impedance fluctuations exceeding ±10% and closed eye diagrams in high-speed signals.
Excessively loose tolerance specifications: Dielectric thickness tolerance of ±0.05mm and trace width tolerance of ±0.02mm can cause impedance deviation beyond specification.
Inner signal layers too far from reference planes: Unbalanced dielectric thickness above and below a stripline leads to unstable impedance and increased crosstalk.
Home > 
