For hardware engineers, mastering reflection suppression isn't just about theory—it's about accurately identifying the high-frequency, impedance-disrupting scenarios that lurk in PCB design details. These scenarios are often hidden in layout and routing intricacies, and a single oversight can turn them into hotspots for signal reflection, leading to severe signal integrity issues.

A common reflection source is the abrupt change in trace width. Engineers often adjust trace widths to navigate around components or vias, a fundamental yet easily overlooked mistake. As discussed earlier, the characteristic impedance of a transmission line is directly tied to trace width. A sudden increase in width raises the per-unit-length capacitance, lowering impedance; a sudden decrease raises it. Such width variations create impedance discontinuities, directly triggering signal reflections. Industry-standard design guidelines mandate that high-speed signal traces maintain consistent width throughout, barring precise impedance tuning. Arbitrary width changes are strictly prohibited.

Trace corners are another common reflection culprit. Right-angle corners are a major red flag in high-speed routing for two reasons: first, the outer edge of a right-angle corner naturally widens, reducing impedance and creating a discontinuity; second, the corner point introduces additional parasitic capacitance, exacerbating impedance mismatch and prolonging signal rise time. For signals exceeding 1Gbps, right-angle corners must be avoided—opt for 45° miters instead. For ultra-high-speed signals (e.g., above 10Gbps), rounded corners with a radius at least three times the trace width are recommended to minimize impedance fluctuations.

In multilayer PCB designs, vias are essential for interlayer connections but are also a primary source of reflection for high-speed signals. The root cause lies in the inherent parasitic capacitance and inductance of vias, which cause their impedance to deviate significantly from the transmission line’s characteristic impedance. Parasitic capacitance, stemming from coupling between pads and antipads, lowers via impedance; parasitic inductance, from the via barrel metal, raises it. Combined, these effects can cause a 10%–30% impedance mismatch, triggering strong reflections.

Even more critical is the reflection issue caused by via stubs. For example, in an 8-layer PCB, if a signal travels from the top layer (Layer 1) to Layer 3 via a through-hole via, the portion of the via from Layer 3 to the bottom layer (Layer 8) becomes an electrically unconnected stub. This stub acts like an open-circuited transmission line in parallel with the main line. When the stub length exceeds 1/20 of the effective wavelength corresponding to the signal’s rise time, it induces severe resonance and intense reflections, distorting the signal waveform. For ultra-high-speed signals like DDR5 and PCIe 4.0+, via stubs are particularly detrimental. Back-drilling is essential to remove unused stubs, keeping stub lengths under 8 mils to effectively suppress reflections.

Parasitic inductance and capacitance in chip packages—from pads, bond wires, and pins—can create impedance mismatches between the chip’s I/O and the transmission line, forming reflection points. Many engineers focus solely on PCB trace impedance in simulations, overlooking package parasitics, leading to significant discrepancies between simulation and actual test results.

Board-to-board interconnects like connectors, headers, and edge fingers are also critical reflection points. Their physical dimensions, pin spacing, and contact methods can cause abrupt impedance changes. Standard pin headers, for instance, have high parasitic inductance and can induce noticeable reflections at speeds above 500Mbps. For high-speed interconnects, impedance-controlled, high-speed connectors are essential. Designers must also optimize pad fanout and implement impedance compensation to minimize fluctuations. Additionally, test pads added to high-speed traces for debugging can create impedance discontinuities. The correct approach is to use stubless test points integrated directly into the trace, avoiding branched test pads altogether.

The characteristic impedance of a transmission line is defined by both the trace and its adjacent reference plane. High-speed return currents flow along the reference plane directly beneath the trace, ensuring impedance continuity. When a high-speed trace crosses a gap between power and ground planes—a “split plane”—the return path is interrupted. Return currents are forced to detour, lengthening the path and drastically increasing loop inductance. This causes a sudden impedance change, triggering strong reflections and significant EMI issues.

Most signal reflections in PCB design stem from impedance discontinuities in these detailed scenarios. Engineers often invest considerable effort in termination matching, only to undermine reflection suppression with a single via stub, a split-plane crossing, or a right-angle corner.