I. Core Differences Between Layout/Routing with Blind/Buried Vias and Traditional Through-Hole Boards
Traditional 6-layer through-hole boards rely on plated-through holes (PTHs) for interlayer transitions, offering complete return paths and straightforward design control. In contrast, 6-layer boards with blind and buried vias utilize segmented microvias for interconnection. The return paths for signals and power traces are fragmented by ground planes and via structures. If traces cross split planes or vias are arranged haphazardly, return paths are forced to detour, increasing loop areas and exacerbating electromagnetic radiation and crosstalk. Furthermore, vias are densely concentrated in BGA areas; high-density fan-out routing is prone to length mismatch, coupling, and impedance discontinuities. High-speed differential buses—such as Automotive Ethernet, USB 3.0, and CAN FD—demand stringent continuity and precise length matching.
The design sequence must shift from the conventional "place components first, then vias" to "lock blind via locations first, partition functional blocks second, and route layer-by-layer last." Using a standard 6-layer 1+4+1 stack-up (L1 Signal / L2 Ground / L3 Inner Signal / L4 Power / L5 Ground / L6 Signal) as a reference:
Top-layer traces reference the L2 ground plane via L1-L2 blind vias.
Bottom-layer traces reference the L5 ground plane via L6-L5 blind vias.
Inner-layer L3 traces reference the L2 ground and L4 power planes.
Buried vias connect L2, L4, and L5 for power and ground distribution.
Based on this hierarchy, specific rules for component placement zones, via arrangement, and differentiated routing standards for three types of nets are established to suit the structural characteristics of blind/buried vias.
II. PCB Zoning and Component Placement Specifications Based on Via Distribution
The PCB is divided into four distinct zones: BGA High-Density Area, Power Section, Analog Acquisition Area, and External Interface Area.
Center Zone: Place main controllers (FPGA/MCU) and high-speed memory chips centrally. Concentrate blind and via-in-pad (VIP) structures here for pin escaping. Reserve ample space on the periphery for trace routing. Keep high-interference heat sources (power inductors, MOSFETs) at least 4mm away from BGAs.
Perimeter Zone: Locate power devices, DC-DC converters, and terminals along the board edges. Use standard buried or through vias for power loops to conserve surface-layer blind via resources. Edge placement also facilitates better heat dissipation, reducing thermal aging stress on microvia plating.
Analog Area: Position sensitive analog circuits away from dense via fields. The periodic metal structure of via arrays radiates EMI, interfering with millivolt-level signals. Route analog traces on a single layer whenever possible. If layer changes are unavoidable, use standard buried vias far from BGA arrays.
Interface Area: Group connectors and communication ports on one side. Place filter and protection components immediately adjacent to interface pads. Utilize surface-layer blind vias to connect to the L2 ground plane for rapid ESD and surge dissipation.
Critical Plane Rules:
Maintain an unbroken L2 ground plane beneath BGAs.
Split the L4 power plane only where absolutely necessary for power isolation.
Ensure continuous ground reference planes beneath all blind vias to stabilize signal returns.
Avoid placing high-mass components (bulk electrolytics, large inductors) over dense via fields to prevent solder joint stress fractures caused by microvia pad pulling during reflow.
III. Routing Control for High-Speed Differentials, General Signals, and Power Nets
1. High-Speed Differential Signal Routing
Layer Preference: Prioritize routing differential pairs on the outer layers (L1/L6) as microstrip lines. Use blind vias for layer transitions.
Symmetry: Both traces in a pair must use the same number and location of vias to prevent length mismatches. Intra-pair length mismatch must be controlled to < 5 mils.
Clearance: When routing near via arrays, maintain parallelism and spacing. Keep vias at least 5 trace widths away from differential pairs to minimize impedance disturbances.
Reference Plane: Ensure a solid reference plane. Do not create anti-pads in the ground plane beneath differential pairs. Optimize blind via pad openings for shielding and safety.
Restriction: Prohibit routing differential pairs through buried vias to the inner layer (L3). The complex reference environment on L3 causes significant impedance fluctuations and crosstalk.
2. General Digital Signal Routing
Via Count: Limit layer transitions to one blind via per net segment; keep total vias per signal path to ≤ 2.
Decoupling: Place 0402 decoupling capacitors immediately adjacent to every blind via. Connect the capacitor ground pad directly to the via's thermal relief to suppress high-frequency noise.
Spacing & Arrangement: Adhere to the 3W rule for parallel traces. Stagger blind vias rather than aligning them in rows or columns to reduce capacitive coupling.
3. Power and Ground Network Design
Distribution: Utilize the L4 power plane for multi-rail distribution. Route power from the surface layer to the ground plane via blind vias, then up to L4 via buried vias.
Impedance: Widen main power trunks. Deploy arrayed grounding vias (blind and buried) to construct a low-impedance power delivery network (PDN).
Loop Control: Place power pins' blind vias adjacent to ground vias to minimize loop area and reduce ripple.
Copper Pouring: Distribute ground vias evenly across large copper areas (2–3 vias per cm²) to ensure ground uniformity and dissipate static charge.
IV. Post-Routing Simulation Verification and Optimization for Blind/Buried Vias
SI Simulation: Perform Signal Integrity analysis. Focus scanning impedance profiles at every blind via location. Adjust via pad sizes and trace widths at points of impedance discontinuity.
PI Simulation: Conduct Power Integrity analysis on the PDN, specifically checking impedance in via-dense areas. Optimize decoupling capacitor placement based on results.
Routing Hygiene: Standardize all trace corners to 45° angles or arcs. Avoid right-angle bends, especially in conjunction with vias, to mitigate signal reflection.
Output Files: Generate separate drill files for blind and buried vias. Include distinct aperture reports and clearly annotate special process requirements (e.g., via filling, via-in-pad).
By leveraging partitioned layout to isolate interference and layer-specific routing tailored to microvia return paths, designers can maximize the density advantages of 6-layer blind/buried via technology while ensuring robust signal quality for high-speed circuits.
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