Following the completion of stack-up design and impedance parameter calculations, the implementation details during the routing phase directly determine whether the physical impedance of the multi-layer board meets technical requirements. Many engineers receive feedback from fabrication houses stating that despite drawing traces strictly according to calculated widths, Time Domain Reflectometry (TDR) tests still show impedance deviations. The issue often lies not in the trace width value itself, but in the destruction of the transmission line environment during routing: crossing split reference planes, variations in intra-pair coupling distance, interference from large copper pours adjacent to impedance lines, and impedance discontinuities caused by vias. This document outlines practical technical requirements for routing single-ended and differential impedance in multi-layer boards to avoid common design pitfalls.

Single-ended 50Ω impedance is widely used for DDR data, address, and clock lines. First, the reference plane beneath the impedance trace must be continuous throughout its length; crossing ground plane slots or split gaps is strictly prohibited. Once a trace crosses a split slot, the signal return path is forced to detour, altering the transmission structure, causing impedance jumps, and triggering signal reflections. Second, maintain a safe clearance between the impedance trace and adjacent copper or pours. Large copper areas must not be placed too close to the impedance line, as excessive coupling capacitance will alter the transmission line impedance. A general rule requires a distance of ≥3 times the trace width between the impedance line and adjacent copper pours. Trace width must remain constant and must not switch arbitrarily (e.g., wide in one segment and narrow in another); abrupt width changes create impedance discontinuities. If layer changes are necessary, use paired vias and ensure the new layer also provides a complete reference plane. Furthermore, minimize branch (T-junction) connections on impedance lines, as T-branches create impedance discontinuities; high-speed signals should avoid branched topologies.

Differential impedance is not merely the sum of two 50Ω single-ended lines; it is jointly controlled by the single-ended impedance of each line and the degree of coupling between them. Technical requirements for differential impedance include the target differential impedance value, as well as control over the single-ended impedance of each line within the pair. Many engineers focus solely on the differential value while ignoring the consistency of the single-ended impedances; intra-pair impedance imbalance generates common-mode noise, often leading to EMI test failures. The two traces within a differential pair must maintain a constant coupling gap; spacing must not vary locally (neither widening nor narrowing). Prioritize 45° bends for turns; avoid acute or right angles. Do not locally increase or compress the intra-pair spacing. Route differential pairs on the same layer whenever possible; avoid switching to different signal layers mid-route. If a layer change is unavoidable, use symmetrically placed vias with identical parameters to ensure environmental symmetry for both paths. The reference plane beneath the differential pair must not be split, and differential signals must never cross plane split gaps. Intra-pair length matching is a technical metric parallel to impedance control; skew must be kept within specification. Crucially, when applying serpentine traces for length compensation, do not alter the intra-pair coupling spacing. Some engineers inadvertently increase spacing in the serpentine section to accommodate the meanders, causing local differential impedance drift.

Multi-layer boards extensively use through-hole, blind, and buried vias. Via pads and anti-pads alter the local transmission structure, creating impedance dips (discontinuities). Vias are high-risk points for impedance control failure in high-speed designs. Oversized via pads or insufficient anti-pad clearance reduce local impedance, while excessively large anti-pads increase it. For high-speed impedance-critical signals, via pad and anti-pad dimensions must be evaluated through impedance simulation. For differential vias, the anti-pads for both vias must be symmetrical to prevent impedance mismatches between the two lines. At very high signal rates, via stubs degrade signal integrity. Back-drilling must be employed to remove these stubs, and back-drilling requirements must be explicitly included in the impedance control specifications. When routing impedance lines into BGA fan-out areas, ensure the via anti-pads do not compromise the integrity of the reference plane.

Component pads are typically wider than impedance traces, presenting a capacitive load at the pad location that causes a local impedance drop. In multi-layer design, do not abruptly widen the impedance trace to the full pad width when connecting to IC pads; use a tapered transition if space permits. In BGA fan-out areas, short fan-out segments leading from the pad will deviate from the nominal impedance. Control the fan-out length to minimize the extent of this discontinuity. In HDI structures, via-in-pad (VIP) technology also introduces local impedance distortion; use VIP cautiously for high-speed impedance-controlled signals. Many engineers focus solely on the impedance of long main routes, neglecting local distortions at component pads, fan-outs, and vias. Even if the main trace impedance is correct, these local discontinuities can cause system bit errors.

Complete the following impedance routing checklist before releasing the design to fabrication:

Impedance control in multi-layer PCBs is a systematic engineering task. It involves more than just setting the trace width; the routing environment, reference planes, vias, and pads all impact the final impedance performance. Strict adherence to routing technical specifications is essential to ensure the physical board meets impedance targets.