In the traditional server era, a 14–20 layer motherboard prototype cost only a few thousand yuan. Today, a compute board prototype for an AI server routinely runs tens of thousands of yuan, and the unit price of a 78-layer orthogonal backplane has broken past 20,000 yuan — a gap of more than tenfold. The first question many engineers ask is: it's just a few more layers, so why has the price exploded? The reality is that layer count growth in AI PCBs is not a linear stacking of layers, but a leap in manufacturing paradigm. Every step up in layer range brings an exponential rise in process difficulty, equipment requirements, and scrap cost.
I. The Layer-Count Leap: From "Circuit Board" to "Semiconductor-Grade Substrate"
Traditional general-purpose server PCBs typically run 14–20 layers, built with conventional through-hole processes and ordinary FR4 materials. The overall manufacturing logic is not fundamentally different from a consumer-electronics motherboard — just larger in scale. With the arrival of the AI computing era, GPU parallel computing and high-speed SerDes interconnects have placed extreme demands on routing density and signal integrity, directly driving a non-linear jump in PCB layer counts.
Take NVIDIA's platform evolution as an example: the H100 generation used a 16–18 layer HDI compute board; the Blackwell platform moved to 20–22 layers; the 2026 Rubin platform reaches 26-layer HDI for the compute board and 44 layers for the midplane backplane; and the next-generation Rubin Ultra orthogonal backplane will soar to 78 layers. This is no longer a printed circuit board in the traditional sense — it is precision manufacturing approaching the level of a semiconductor packaging substrate.
The cost increase from more layers is by no means a linear "add X yuan per layer" calculation. Every two additional layers mean one more core lamination, one more alignment step, and one more round of drilling and metallization. A 44-layer board requires more than ten lamination cycles, and each lamination must maintain interlayer alignment accuracy of ≤25μm — far tighter than the ±50μm standard for conventional boards. The more lamination cycles, the higher the risk of interlayer misregistration, uneven resin flow, and board warpage, with material loss and scrap rates rising in tandem.
II. HDI Order Escalation: The Cost Barrier from Through-Hole to 8th-Order Blind/Buried Vias
If layer count is vertical scaling, then HDI (High Density Interconnect) order is horizontal density scaling — and it is the core driver behind the surge in AI PCB cost. Traditional server motherboards mostly use 1st–2nd order HDI or an all-through-hole process, which hundreds of factories worldwide can produce. AI compute boards, by contrast, generally use 5th–8th order HDI, and fewer than ten manufacturers worldwide can mass-produce them.
A higher order means an exponential increase in blind/buried via process complexity. First-order HDI requires only one laser drilling and filling cycle; 8th-order HDI requires eight "drill – metallize – fill – laminate" cycles, and every cycle can introduce defects. Laser-drilled hole diameters have shrunk from 0.15mm to 0.075mm, placing extremely high demands on drilling equipment precision and stability; a high-end laser drilling machine costs several times more than an ordinary drill.
More critical is the cliff-edge drop in yield. Drilling yield for ordinary through-hole boards is close to 100%, first-order HDI can exceed 95%, but for 8th-order HDI the drilling yield drops 3–5 percentage points with each additional order, leaving overall yield potentially below 70%. In other words, three boards must be produced to get one good one, and the cost of the two scrapped boards is fully amortized into the qualified product — directly inflating the final unit price.
III. High-Density Routing: Narrower Line Widths Force a Full Equipment Overhaul
The ultimate purpose of increasing layer count and HDI order is to achieve higher routing density and support the transmission of massive volumes of high-speed signals. Traditional server PCBs typically use 5mil (about 127μm) line width/spacing, while AI PCBs have narrowed to 2–3mil (50–75μm), with some high-speed serial channels even reaching the 1mil (25μm) level.
Shrinking line widths marks the limit of the traditional subtractive etching process. Conventional whole-panel etching suffers severe undercut below 3mil, producing trapezoid-shaped trace cross-sections that make impedance consistency impossible to guarantee. AI PCBs must adopt the mSAP (modified Semi-Additive Process), forming circuits through seed-layer sputtering, photolithographic patterning, and copper electroplating — delivering finer line widths and more vertical sidewalls.
But the equipment investment and material cost of mSAP are far higher than those of conventional processes. It requires new sputter-coating equipment and high-precision lithography exposure machines, nearly doubles the number of process steps, and lengthens the production cycle. At the same time, fine circuitry demands extremely tight control of copper foil surface roughness, dry-film resolution, and etchant concentration — any parameter fluctuation can cause batch scrap. This is also why so many traditional PCB makers cannot pivot to AI boards: it is not that they don't want to, but that the cost of retrofitting production lines and the technical barriers are simply too high.
Conclusion
The high price of AI PCBs is essentially a generational leap in process grade — an upgrade from traditional general-purpose manufacturing to semiconductor-grade precision manufacturing. Every improvement in layer count, HDI order, and routing density corresponds to a compounding of equipment, material, and yield costs.
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